The present invention relates to an electrostatic discharge (ESD) protection structure, and more particularly, to an ESD protection structure having the modified lateral silicon controlled rectifiers (MLSCR) by using a resistance capacitance (RC) circuit to distinguish an ESD event from an overshoot phenomenon caused by an instantaneous power-on.
While two nonconductors are either approaching or separating, a very possible result is electrons being transferred between these two nonconductors, with which excess charges called electrostatic charges being induced. When electrostatic charges accumulated on an object are discharged into the other object having relatively low voltage, a so-called ESD phenomenon is induced. Generally, the formation of ESD can be divided into a direct type and an indirect type, wherein the direct type means that an object directly contacts the other object on which charges are induced by friction, and the indirect type means that the object is charged by the induction resulting from the change of surrounding electricity.
However, while metal pins of an integrated circuit (IC) are in contact with an object having electrostatic charges, instantaneous high-voltage charges are generated and affect the inner circuit through the metal pins. It can be known from the above description that ESD is one of the major potential factors causing the failure of an electronic system. On the other hand, a metal oxide semiconductor (MOS) transistor with the characteristic of high impedance is easily to be damaged by the influence from ESD. As the complexity of semiconductor increases, the sensitivity of the sub-micron process and extremely narrow line-width to instantaneous over-voltage also has to be raised. A voltage of only about 15 volt (V) to about 20 V is all that is needed to damage the gate oxide layer of the MOS transistor, and the peak value of ESD pulse often reaches thousands of volts. Hence, for enhancing the reliability of an electronic device, an ESD protection device has to be installed into an electronic device to avoid the electronic device from being damaged by an ESD event.
Recently, the ESD protection device comprises a resistor, a diode, a MOS transistor having a thin oxide layer, a device having a thick oxide layer, a parasitic bipolar junction transistor (PBJT), a parasitic lateral silicon controlled rectifier, and a combination of the devices described above. The following description is the operating principle of an ESD protection circuit using the P-type MLSCR.
Referring to FIG. 1, a cross-sectional view of a conventional ESD protection structure having a P-type MLSCR is shown. On a P-type substrate 100, there are an N-well 102, an N-type diffusion 112, a P-type diffusion 114, and a P-type diffusion 110 formed, wherein the N-well 102 further comprises an N-type diffusion 106 and a P-type diffusion 108. The P-type diffusion 110 is located between the N-well 102, and the P-type substrate 100. The P-type diffusion 108 located in the N-well 102 is an anode of the P-type MLSCR 118, and the N-type diffusion 112 located in the P-type substrate 100 is a cathode of the P-type MLSCR 118.
P-type MLSCR 118 can be considered as two individual bipolar transistors, which are a PNP transistor composed of a P-type diffusion 108, an N-well 102 and a P-type diffusion 110, and an NPN transistor composed of a P-type diffusion 110, a P-type substrate 100 and an N-type diffusion 112. FIG. 2 is a diagram showing the curve of operation current I vs. operation voltage V for a conventional ESD protection structure having a P-type MLSCR. With reference to this figure, the operating principle of the P-type MLSCR 118 used as protection device is as follows. P-type substrate 100 is connected to ground, a voltage is applied to the pad 104 of an IC. When the ESD event occurs, holes are injected into the N-well 102 from the P-type diffusion 108, so that a forward bias is induced to turn on the PNP transistor. Meanwhile, current flows through the PNP transistor into the P-type substrate 100, and thus the forward bias is applied to the NPN transistor to also turn on the NPN transistor. The induced electrons flow into the PNP transistor, and flow through the cathode to ground. Since a forward bias is applied to the PNP transistor with the electrons flowing through, a bias is no longer needed for the PNP transistor, and the voltage of the MLSCR is called a trigger voltage VT. Then the applied voltage is decreased gradually to a minimum value, and the minimum value is called a holding voltage VH.
According to the above description, when the voltage released from ESD is bigger than the trigger voltage of SCR, the charges released from ESD are guided away by the SCR to protect the device from damage caused by ESD. However, when the SCR is triggered accidentally, for example, by an overshoot phenomenon induced by turning on power suddenly, the duration of ESD is far less than that of turning on power, and the voltage VP is supplied uninterruptedly after power is turned on. Since the SCR misjudges a power-on event as an ESD event, the SCR increase the current I continuously to catch up with the applied voltage VP, and eventually the SCR is burned out due to overheating, as shown in FIG. 3.
Since there is only a small difference between the voltage to be distinguished and the trigger voltage of the MLSCR in the aforementioned conventional ESD protection structure, for example, the voltage induced by an overshoot phenomenon caused by turning on power, the overshoot phenomenon and the electrostatic event are hardly distinguished from each other effectively by the ESD protection structure, so that the MLSCR is improperly triggered to cause the damage of the ESD protection structure.
One of the major objects of the present invention is to provide an ESD protection structure, and the present invention is to implement a RC circuit on the ESD protection structure having, for example, a P-type MLSCR. Time constant of the RC circuit is adjusted to the one between ESD pulse time and power-on time of normal operation, so as to distinguish an ESD event from an overshoot phenomenon caused by turning on power, and thereby to avoid the SCR being triggered improperly and the damage of the ESD protection device.
The further object of the present invention is to provide an ESD protection structure, and the present invention is to implement a RC circuit on the ESD protection structure having, for example, a P-type MLSCR. Time constant of the RC circuit is adjusted to the one between ESD pulse time and power-on time of normal operation, thereby forcing most of the SCR current to flow to a substrate and thus lowering a trigger voltage of the SCR, so that the damage due to an accidental triggering can be avoided and the efficiency of ESD protection device is promoted.
Based on the objects described above, the present invention is to provide an ESD protection structure mainly comprising a MLSCR, a MOS transistor, and a RC circuit, wherein the MLSCR comprises a P-type substrate, an N-well formed in the P-type substrate, a first N-type diffusion and a first P-type diffusion located in the N-well, a second P-type diffusion located between the N-well and the P-type substrate, and a second N-type diffusion and a third P-type diffusion located outside the N-well. Time constant of the RC circuit is set in the rank of 10xe2x88x926 second (xcexcs), and the first N-type diffusion and the first P-type diffusion are connected to a pad, and the second N-type diffusion and the third P-type diffusion are connected to ground. When an ESD event occurs, the pulse time of ESD is so short in the rank of 10xe2x88x929 second (nanoseconds; ns) that the RC circuit cannot respond in time, which results in a near 0 V gate voltage of the MOS transistor connected to the RC circuit, and hence the MOS transistor stays in a closed state, thereby lowering the trigger voltage of MLSCR. However, while in normal operation, since normal power-on duration belongs to the rank of 10xe2x88x923 second (milliseconds; ms), the voltage of normal power-on can be guided to the gate of MOS transistor by the RC circuit so as to turn on the MOS transistor, and hence part of the current flows through the second P-type diffusion into the MOS transistor and then to ground, and the trigger voltage of the MLSCR is further raised. According to the above description, with the application of ESD protection structure of the present invention, the trigger voltage of ESD event of the MLSCR can be lowered, and the trigger voltage of normal power-on of the MLSCR can be enhanced. With the different trigger events, the difference of trigger voltage between these two aforementioned situations is enlarged, and therefore the ESD event and the normal power-on event can be distinguished from each other effectively, so that the object of enhancing the efficiency of ESD protection device can be obtained.